Recently I added some logic gates to my synthesiser. Not the familiar little chips we know and love

rather, logic gates especially for musical application.

I’ve had an OR gate in my synth from the early days, finding it useful for combining trigger signals from my sequencer to build up drum patterns, etc. Originally, I used the simplest diode-based OR gate designs, such as that as seen on the Doepfer DIY page. Subsequently, I augmented this with a level converter, to allow the OR gate to trigger those modules requiring high voltage signals (I still have some old MFOS modules expecting 10V) even when the sources were putting out timid 5V pulses from a microcontroller. I exploited the same old level converter circuit I’ve used and abused many times before.

This original OR gate worked but wasn’t everything I wanted, so I started to toy with a new design and realised it was easy to conceive of an AND sibling for my new OR gate, as they shared many common features.

**New AND Module operating on two square waves at 2:1 frequency ratio**

**Figure 1 AND of Square Waves recorded in PulseView, Ta=4, Tb=2**

**Figure 2 OR of Square Waves recorded in PulseView, Ta=4, Tb=2**

### Some observations on modulation

% Specify the Periods of the two squarewaves:Ta=10;Tb=12;% Specify the duty cycles of the two squarewaves:DUTYa=50;DUTYb=50;% Calculate the normalised frequencies of the two squarewaves:fa=1/Ta-eps;fb=1/Tb-eps;% Generate a time vector:tmax=1000;t=[0:tmax];% build the squarewaves:a=(square(fa*2*pi*t,DUTYa)+1)/2;b=(square(fb*2*pi*t,DUTYb)+1)/2;% apply the logic:c=and(a,b);d=or(a,b);e=xor(a,b);% Now look at the result in the Frequency Domain:% build a window:w=window(@blackman,length(a)).';% and calculate the FTsA=fft(w.*a);B=fft(w.*b);C=fft(w.*c);D=fft(w.*d);E=fft(w.*e);

**Figure 3: Square Waves a, b, (Ta = 8, Tb = 10) modulated by AND and OR gates**

**Figure 4: Magnitude Spectra of Square Waves a, b, (Ta = 8, Tb = 10)**

**modulated by AND and OR gates**

*f*n, (running from

*f*n = 0 to the Nyquist Frequency,

*f*n = 0.5).

**Figure 5: Comparison of the Magnitude Spectra of the outputs of the AND and OR gates**

**when fed by Square Waves a, b, (Ta = 8, Tb = 10)**

*f*n = 0 (d.c. as electrical engineers call it).

So I set the duty cycle of both pulse outputs as best I could to 50% and – yes – the sound of the OR and AND gate modulating the same pair of square waves suddenly sounded similar – just as the code predicted.

**The outputs of the AND and the OR modulators sounded the same!!**

**Figure 6: Comparison of the Magnitude Spectra of the outputs of the AND and OR gates**

**when fed by Rectangular Waves a, b, (Ta = 8, Tb = 10, DUTYa = DUTYb = 40)**

* the result of modulating two rectangular signals by an AND gate sounds different to the result of modulating the same pair of rectangular signals by an OR gate (no surprise)but* there are special circumstances (in the case of SQUARE waves with truly 50% duty cycle), where modulation by AND and OR produces the same magnitude spectrum (apart from the d.c. term).

[because these (1.1 and 1.2) will only change the phase component of the spectral peaks associated with the harmonics of the periodic signal – not their magnitude, and will not change the peak at d.c (fn = 0)]

[because these (2.1 and 2.2) will impact the peak at d.c. (fn = 0 ) but not the other harmonic peaks, which are agnostic to mean value and phase/polarity]

**Figure 7: Comparison of the AND and (negated) OR gates' outputs**

**when fed by Square Waves a, b, (Ta = 8, Tb = 10)**

[It also mightappearthat there's some time-shift involved too, but - as I'll show below - time shift isn't involved. In fact, there's no memory/filtering/delay mechanism in the modulator capable of imposing a time shift; it's all in the signals - but we're getting ahead of ourselves.]

*quite*hold. For, where they don’t quite hold, there are some fascinating possibilities for pattern generation. That's for another day. For now, I must limit myself to...

### Explaining the Curiosity

__over the period of the output of modulator__, which is to say, over a period of T0, where:

**Update**[3 May 2023]

**when fed by Square Waves a, b, (Ta = 8, Tb = 10), demonstrating antipalindromic property**

**Figure 9: Inputs (and 'flipped' inputs) to the AND and negated OR gates**

**when fed by Square Waves a, b, (Ta = 8, Tb = 9), input b is NOT antipalindromic**

**Figure 10: Output of the AND and (negated) output of the OR gate**

**when fed by Square Waves a, b, (Ta = 8, Tb = 9)**

*what is now*) UCL. This man, who gloried in the given name Augustus, formulated a pair of laws important to searching and fundamental to the simplification of logic networks. The laws honour his family name: ‘De Morgan’s Laws’ and used to be a mainstay of undergraduate digital courses in electronic engineering programs everywhere, along with Karnaugh maps, ‘minterms’, Sum-of-Product solutions and all the rest. I used to teach this stuff back in the 1980s.

"The negation of a disjunction is the conjunction of the negations""The negation of a conjunction is the disjunction of the negations"

__second__simplest example I can conceive of (I would show you the simplest example but it's too trivial, so I’ll leave that to you).

**Figure 10: Inputs and flipped inputs to the AND and OR gates**

**when fed by Square Waves a, b, (Ta = 4, Tb = 2), demonstrating antipalindromic property**

**Figure 11: Inputs and flipped inputs to the AND and OR gates**

**when fed by a repeated sequence [1, 0, 1, 1, 0, 0, 1, 0], a, and a Square Wave, b, (Tb = 2)**

*f*n = 0):

**Figure 12: Comparison of the Magnitude Spectra of the outputs of the AND and OR gates**

**when fed by**

**a repeated sequence [1, 0, 1, 1, 0, 0, 1, 0], a, and a Square Wave, b, (Tb = 2)**

**Figure 13: Output of the AND and (negated) output of the OR gate**

**when fed by**

**a repeated sequence [1, 0, 1, 1, 0, 0, 1, 0], a, and a Square Wave, b, (Tb = 2)**

### Covering the Exclusive Base

**Figure 14: Magnitude Spectra of Square Waves a, b, (Ta = 8, Tb = 10)**

**modulated by AND, OR, and XOR gates**

*i.e. add an offset*) and apply lag (

*i.e. impose first order filtering*) to a voltage signal passed through it. Most importantly to the present application, if you keep on dialling down the attenuation control it turns into an inverter; an ‘attenuverter”. Voila – the Voltage Processor becomes a NOT gate.

[It is also ‘two layer’; you have to do the ANDs first before the OR, so it literally takes longer than the single layer AND and OR operations.]

*some*significance in

*some*area and is probably already widely known and widely described - there is, after all, "nothing new under the sun".

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